Austin, Texas, United States
Summary
Posted: Sep 11, 2024
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!
Description
You will apply your hand-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. Primary Responsibilities will include: – Develop and improve existing flows for Physical Synthesis, LEC and DFT Implementation – Support multiple design teams and work with cross functional teams to integrate solutions in different flows – Collaborate (or partner) with cross-functional teams to solve key FE methodology challenges – Developing innovative solutions in physical synthesis and DFT implementation space – Developing and maintaining custom CAD tools for synthesis and DFT implementation – Developing flows/methodologies for better PPA and productivity including ML based solutions – Collaborate with tool vendors to resolve tool issues and drive PPA improvement opportunities in tool
Minimum Qualifications
- Experience with TCL, Python or Perl scripting languages
- Experience with industry standard Synthesis tools such as Fusion Compiler or Genus
- Experience working with CAD Tools & flow
- Minimum requirement of BS + 10 years of relevant industry experience
Preferred Qualifications
- Demonstrated experience in CAD flow or FE Methodology development
- Ability to analyze RTL structures and identify optimization opportunities is preferred
- Experience with Low Power implementation flows (UPF) is a plus
- Experience with logical equivalence tools such as Conformal LEC and/or Formality is a plus
- Experience in linting, static timing analysis, low power checks (UPF) or place and route tools is a plus
- Proficiency with TCL, Python or Perl scripting languages strongly preferred