Austin, Texas, United States
Summary
Imagine working in a team where the only limits are the laws of physics and your imagination. At Apple, great ideas have a way of becoming great products and customer experiences very quickly! Bring passion and dedication to your job and there’s no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices. Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!
Description
You will work closely with the RTL and PD (physical design) teams and be responsible for synthesis, analysis, and optimization of the delivered IP. For this role, you will use and develop advanced techniques to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Minimum Qualifications
- – We seek individuals with expert design experience to understand RTL design principles and drive quality physical design implementation.
- – Experience with owning partition level implementation to drive analysis and optimizations using advanced synthesis techniques and RTL design improvement for optimal Area, Timing Power.
- – Experience with Physical Design and Timing Analysis teams on physical concepts like floor-planning, structured placement, congestion, and timing constraints.
- Experience on analyzing architectural critical paths and drive multi-block closure across RTL Design and Physical Design teams.
- Experience on debugging complex logic equivalence issues and review netlist checks to validate functionality and netlist quality.
- Experience on developing and driving adoption of innovative methodologies.
- Experience implementing ECOs for functionality and timing.
- Experience with one or more of: structured placement, memory optimization, reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level.
- Relevant scripting experience in ASIC flows – python, tcl, Perl, Data manipulation.
- BS + minimum of 15 years of experience.
Preferred Qualifications
- Ability to solve complex problems across multiple technical domains.
- Familiarity with DFT insertion.
- Experience with Memory/Latch/Regbank optimization.
- Familiarity with simulation, debugging tools and experience of working closely with design verification team.
- Experience working on GPUs is desirable.