SoC DFT Engineer

by

Beaverton, Oregon, United States

Summary

Do you love crafting sophisticated solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, you will be at the center of a semiconductor design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly.

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Description

As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. – Developing and implementing DFT architecture – Implementing DFT infrastructure – Working with the DV team to verify DFT implementations and implement ECOs – Generating structural test vectors and analyzing and improving coverage – Working with designers on STA, physical, power and logical issues – Working with test engineers to bring up test vectors on silicon – Running schedules and supporting multi-functional engineering efforts

Minimum Qualifications

  • BS and a minimum of 10 years relevant industry experience

Preferred Qualifications

  • Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
  • Experience developing DFT specifications and driving DFT architecture and methods for designs.
  • Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools.
  • Knowledge of industry standards for DFT and design tools.
  • Proven Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon.
  • Experience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues.
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations.
  • Ability to conduct experiments during silicon debug, gathering and analyzing data; and use scripting to support efficient handling of ATE data.

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